Silicon on insulator (SOI) technology is a recent approach to providing single crystal silicon on insulating structures. Several methods for making SOI structures are presently available. One successful approach has been to cover a silicon wafer with a layer of an insulating material such as silicon nitride or silicon dioxide, and then to deposit silicon by chemical vapor deposition (CVD) on the insulator to form a polysilicon layer. Next, the polysilicon layer is formed into a single crystal layer by a number of techniques such as Zone Melting and Recrystallization (ZMR).
In one version of ZMR, the polysilicon is seeded by the single crystal silicon substrate whereby seed openings are etched or scribed down to the substrate. A movable strip heater is positioned above the openings and melts the polysilicon through to the subsrate forming a molten zone. The heater is then moved laterally creating a translating molten zone, and single crystal silicon is grown laterally over the wafer as the melted polysilicon recrystallizes due to the molten zone tranlsating along the wafer. An optional encapsulation layer may be formed over the polysilicon film to improve thermal stability of the molten zone and to prevent contamination of the film.
Several problems have been found with the previously described process. The liquid/solid front for recrystallization by the graphite strip heater forms a favorable energy configuration of a faceted front of (111) planes as it advances across the wafer. Thus, the liquid/solid interface morphology and the resulting defect structure and density of the finished SOI product is quite sensitive to small changes in the power applied to the heater or the height of the upper strip heater. If the power, or height, of the strip heater is not favorable, the surface morphology of the resulting crystal suffers from branching of the defect trails or even multigrained growth. These morphologies are not conductive to optimal performance of devices formed in the SOI structure. Additionally, the presence of these defects causes a thickness variation of the recrystallized layer. Elimination of branching, reduction of the defects and thickness variation, and overall improvement of surface morphology would significantly improve the yield and quality of this SOI process.
A method of entraining crystalline defects is presented in U.S. Pat. No. 4,479,846 to Smith et al. As stated in the patent, an added step is required before ZMR processing of the polysilicon on insulator on silicon substrate can be initiated. A layer of material in the form of a pattern of parallel stripes must be added to the substrate. The addition of this pattern of stripes, known as the entrainment pattern, is required carry out the method and contributes additional time, effort and complexity to the process.
Once the entrainment pattern is added to the structure, the Smith invention uses a traditional strip heater which is passed over the structure creating a translating molten zone in the polysilicon. The Smith invention is directed at defect entrainment by the application of an extra layer of material to the wafer before ZMR processing.